Implementation of FPGA-Based RISC for LNS Arithmetic by Software & Hardware


Field Programmable Gate Arrays (FPGAs) have some difficulty with implementation of floating – point operations. In particular, devoting the large number of slices needed by floating- point multipliers prohibit incorporating floating point into smaller, less expensive FPGAs. An alternative is the Logarithmic Number System (LNS) , where multiplication and division are easy and fast. LNS also have the advantage of lower power consumption than fixed point. The problem with LNS has been the implementation of addition . There are many price /performance tradeoffsin the LNS design space between pure software and specialized-high-speed hardware .This paper focuses on a compromise between these extremes. And on a small RISC core design ( loosely inspired by the popular ARM processor ) in which only 4 percent additional investment in FPGA resources beyond that required for the integer RISC core more than doubles the speed of LNS addition compared to a pure software approach . This approach shares resources in the data path of the non –LNS parts of the RISC so that the only significant cost is the decoding and control for the LNS instructions under consideration , are more cost effective than pure software and be as cost effective as more expensive LNS- FPGA implementations that attempt to maximize speed .