REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM

Abstract

For double fields and large code lengths, Low-Density Parity-Check (LDPC) code approachesShannon–limit execution. The goal of this project is to present an LDPC calculation for MinSum (MS) decoding and equipment execution inquiry within a communication frameworkthat has been proposed. The MS calculation principally utilizes the base and expansionfinding ‎procedure. The quantity of increases is subsequently altogether diminished, whichtends to ‎decrease the execution intricacy. The consequences of the reenactment show that theproposed ‎MS interpreting calculation performs the same as the translating of the Sum-ProductAlgorithm ‎‎(SPA) while keeping up with the principle highlights of the MS disentangling. Thefurther developing execution ‎by diminishing the number of stages in the deciphering system,diminishing the intricacy of the ‎implementation of the Field Programmable Gate Array(FPGA).‎

Keywords

LDPC, MS, SPA, Log Domain.