Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software Defined Radio


This paper presents a design and simulation of digital PLL synchronizer, usingCostas loop based on SDR for high frequency communication systems. Designparameters are selected for each unit of the proposed systems in order toaccommodate SDR requirements. Different techniques for carrier recovery basedon SDR are discussed. PLL techniques is chosen for synchronization, since it isone of the most active synchronization techniques. BPSK and QPSKsynchronizers for coherent receivers have been designed and simulated based onSDR using both Costas loop and modified Costas loop. The simulation resultshows that these two systems are reliable in recovering the carrier phase andfrequency when significant frequency and phase are present. Simulation resultshows that the BPSK system has Pe =10-3 at Eb / No equal to 8.5 dB in thepresence of AWGN and has the ability to track frequency offset up to 1200Hzwith 2*10 -4 probability of bit error at Eb / No equal to 20 dB. This system cantrack phase offset 45 o with Pe =10-4 at Eb / No equal to 20 dB. For QPSK system,the probability of bit error 10-3 at Eb / No =9dBand has the ability to trackfrequency offset 300 Hz and phase offset=9 o with Pe =10-3 at Eb / No equal to20dB.