Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity

Abstract

The aim of the present paper is to investigate the minimization of the power consumption in combinational circuits by reducing the switching activity. A synthesis approach based on an iterative procedure that compares the minterms consequently, eliminate the complementary variables, then ORing all the terms in one simplified equation isintroduced . The results show that about 10% reduction in switching activity has been obtained by using this method if it is compared with the normal optimal solution obtained from K-map method.