An Investigation of Electrical Properties of (p-n) Porous Silicon Layer


In this work, we studied the electrical properties of (p-n) porous silicon layer under different etching time. The (p-n) porous silicon layer prepared by photo-electrochemical etching process. The dark I-V characteristics; give us rectification ratio with wide range as a function to etching time. A high value for the rectification behavior is related for etched samples at low etching time. While the increasing of etching time to high value show a non rectification behavior in (p-n) porous samples. The values of the photo-current for (p-n) porous sample at low etching time has very small value compared with the other (p-n) porous silicon samples at high etching time and this behavior in PSi layer in high etching time cannot be employed light emitting diode applications. While the layer prepared at low etching time is well suitable for light emitting device.