TY - JOUR ID - TI - Fast Combined Decimal/Binary Multiplier Based on Redundant BCD 4221-8421Digit Recoding AU - Mohammed Nabil محمد نبيل AU - Fatemah K Al-Assfor فاطمة العصفور AU - Mohammed A. Al-Ebadi محمد العبادي PY - 2017 VL - 17 IS - 1 SP - 40 EP - 47 JO - Basrah Journal for Engineering Sciences مجلة البصرة للعلوم الهندسية SN - 18146120 23118385 AB - Many applications consider floating point arithmeticas a key component of the computations. Combineddecimal/binary arithmetic becomes an important topicsupports high-speed decimal/binary applications. A new 64-bit(16×16 digit) the combined decimal/binary multiplier is proposedand implemented in this work that can be used for both fusedmultiply-add (FMA) and multiplier unit. A new partialproducts reduction tree is shared between decimal and binarymultiplier unit. The valuation and comparison result betweenthe proposed multiplier and the previous most recent worksshows 4.66 % less delay than combined decimal/binarymultiplier and 19.33 % less delay than the fastest standalonedecimal multiplier

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