TY - JOUR ID - TI - A low phase noise gm-boosted DTMOS VCO design in 180 nmCMOS technology AU - Shasanka Sekhar Rout*, Satabdi Acharya, Kabiraj Sethi PY - 2018 VL - 4 IS - 2 SP - 228 EP - 236 JO - Karbala International Journal of Modern Science مجلة كربلاء العالمية للعلوم الحديثة SN - 2405609X 24056103 AB - This paper presents the design of a low phase noise voltage controlled oscillator (VCO), which offers higher transconductance(gm) by the use of parallel MOSFETs. Here, two NMOS transistors are connected in parallel with the cross-coupled NMOStransistors of a conventional cross-coupled VCO. So, the total negative conductance offered to the circuit to cancel out the parasiticresistance of the LC-tank is increased. This negative conductance is achieved without dealing with larger transistor size or any otherpassive elements. Hence, power dissipation and silicon area are reduced. Further, dynamic threshold MOSFET (DTMOS) with acapacitive division technique is implemented to increase the voltage swing, leading to a further decrease in phase noise. Theproposed VCO is designed and simulated in UMC 180 nm technology. It achieves a tuning range of 1.58e1.60 GHz about200 MHz, with 6.09 mW power consumption at 1.1 V supply voltage. The phase noise is obtained40.6 dBc/Hz at 1 kHz and120.44 dBc/Hz at 1 MHz respectively. So, it should be used in transceiver and PLL blocks for low voltage and low phase noiseapplications.

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