TY - JOUR ID - TI - REDUCING LDPC DECODER COMPLEXITY BY USING FPGA BASED ON MIN SUM ALGORITHM AU - Butheena R. kadhim AU - Fatih Korkmaz PY - 2022 VL - 13 IS - 1 SP - 82 EP - 101 JO - KUFA JOURNAL OF ENGINEERING مجلة الكوفة الهندسية SN - 20715528 25230018 AB - For double fields and large code lengths, Low-Density Parity-Check (LDPC) code approachesShannon–limit execution. The goal of this project is to present an LDPC calculation for MinSum (MS) decoding and equipment execution inquiry within a communication frameworkthat has been proposed. The MS calculation principally utilizes the base and expansionfinding procedure. The quantity of increases is subsequently altogether diminished, whichtends to decrease the execution intricacy. The consequences of the reenactment show that theproposed MS interpreting calculation performs the same as the translating of the Sum-ProductAlgorithm (SPA) while keeping up with the principle highlights of the MS disentangling. Thefurther developing execution by diminishing the number of stages in the deciphering system,diminishing the intricacy of the implementation of the Field Programmable Gate Array(FPGA).
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