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Fast Combined Decimal/Binary Multiplier Based on Redundant BCD 4221-8421Digit Recoding

Mohammed Nabil محمد نبيل --- Fatemah K Al-Assfor فاطمة العصفور --- Mohammed A. Al-Ebadi محمد العبادي

Basrah Journal for Engineering Science مجلة البصرة للعلوم الهندسية
ISSN: Print: 18146120; Online: 23118385 Year: 2017 Volume: 17 Issue: 1 Pages: 40-47
Publisher: Basrah University جامعة البصرة

Abstract

Many applications consider floating point arithmeticas a key component of the computations. Combineddecimal/binary arithmetic becomes an important topicsupports high-speed decimal/binary applications. A new 64-bit(16×16 digit) the combined decimal/binary multiplier is proposedand implemented in this work that can be used for both fusedmultiply-add (FMA) and multiplier unit. A new partialproducts reduction tree is shared between decimal and binarymultiplier unit. The valuation and comparison result betweenthe proposed multiplier and the previous most recent worksshows 4.66 % less delay than combined decimal/binarymultiplier and 19.33 % less delay than the fastest standalonedecimal multiplier

Keywords

Multiplier --- BCD 4-2-2-1 --- BCD 8-4-2-1 --- decimal --- binary