DESIGN OF A LOW PASS FIR DIGITAL FILTER USING FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)

Abstract

This paper introduces a design of a low pass finite impulse response digital filter usingfield programmable gate arrays (FPGAs). A fully parallel distributed arithmetic FIRfilter was used to attain speed/ area optimization. . A dual port (4096 x 32) RAM isdesigned to store the filter output samples. The different modules (elements) composingthe system are assembled hierarchically to obtain a hierarchical structure design. Fixedpoint numbers format is used to avoid data width inflation due to successivemultiplication and addition operations. Xilinx integrated software environment(ISE10.1 software) was utilized to develop the VHDL modules. The design could beapplied on Xilinx Spartan3E or Vertix family. The system is tested using ISE simulator.The results obtained are compared with the results achieved by simulating the filter onDSP block set of Mat lab 7.2 version software.