Implementation of Reed-Solomon Encoder/Decoder Using Field Programmable Gate Array

Abstract

In this paper, (15, 11) and (255, 239) Reed-Solomon codes have been designed and Implemented using ALTERA Field Programmable Gate Array (FPGA) device. The design is carried out by writing VHDL modules for different encoder and decoder components. The waveforms are tested using the package MODEL-SIM 5.4a. While synthesis reports and board programming file are obtained using the package QUARTUS II. ALTERA-FLEX10K10 FPGA board is used as a target device for the designed Reed-Solomon encoder/decoder. Simulation waveforms show that (15, 11) and (255,239) Reed-Solomon decoders could correct up to 2 and 8 erroneous symbols respectively