Digital Single Phase Power Factor Optimizer Based on FPGA

Abstract

In this paper, an FPGA (Field-programmable gate array) model of digital singlephase power factor optimizer has been built. The proposed optimizer is based onmeasuring the phase shift time between voltage and current waveforms. Therefore,it is required to reduce this time to make the voltage and current waves in phase aspossible. Thus, the power factor will be in maximum value (closed to unity). Theprocess of improving the power factor is carried out by connecting a set ofcapacitors in parallel with the load. The proposed power factor optimizer has beenbuilt using VHDL (Very high speed integrated circuit Hardware DescriptionLanguage), simulated using Xilinx ISE 9.2i package and implemented usingSpartan-3A XC3S700A FPGA kit. Implementation and Simulation behavioralmodel results show that the proposed optimizer satisfies the specified operationalrequirements and reflected impressive results when applied to different loads.